Metrology processes are used for monitoring and controlling various steps of a semiconductor manufacturing process by measuring parameters of a wafer, such as line width, thickness, angle, etc. As a demand for shrinking semiconductor devices continues to increase, multiple patterning technologies are used for manufacturing integrated circuits (ICs) to enhance the pattern feature density.
A simplest example of the multiple patterning techniques is a double patterning, which allows the patterning of smaller features at a smaller pitch than what is currently possible with standard lithographic techniques. To this end, standard lithographic pattern-and-etch techniques can be applied to the same substrate twice, thereby forming larger patterns spaced closely together to achieve a smaller feature size than would be possible by single exposure. During double patterning, a layer of radiation-sensitive material on the substrate is exposed to a first pattern, which is developed and transferred to an underlying layer using an etching process, and then these standard lithography steps are repeated for a second pattern, while shifting the second pattern relative to the first pattern.
Another approach to double the resolution of a lithographic pattern is to utilize a dual-tone development technique, wherein a layer of radiation-sensitive material on the substrate is exposed to a pattern of radiation, and then a double pattern is developed into the layer of radiation-sensitive material. Such dual-tone development techniques are described for example in U.S. Pat. No. 8,283,111.
In general, multiple patterning lithography process, which may be double, triple, quadruple, etc. patterning process, requires multiple photolithographic masks for the printing of a single layer on a wafer. Therefore, a multiple patterning lithography process adds a new contribution to the overlay error, which is associated with a placement error of two or several masks used to form the pattern for a single layer on the wafer. An overlay error in a pattern generated with a self-aligned double patterning technique is known as “pitch walking” effect.
For example, US patent publication No. 2014/036243 describes a method for correcting at least one error on wafers processed by at least one at least two photolithographic masks used in a multiple patterning lithography process. This method includes measuring the at least one error at a wafer processing site, and modifying the at least one photolithographic mask by introducing at least one arrangement of local persistent modifications in the photolithographic mask. This technique suggests using a so-called hard material photo resist of a sacrificial layer on top of a layer to be etched in a self-aligned double patterning process, and introducing an arrangement of local persistent modifications or the pixels in the sacrificial layer to avoid a variation of the lines during the etching of said layer underneath the sacrificial layer, to thereby prevent “pitch walking” effects during the etching step.